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A S 11 5 6 / A S 11 5 4 S i n g l e / D u a l LV D S D r i v e r
D a ta S he e t
1 General Description
The AS1156/AS1154 is a Single/Dual Flow-Through LVDS (Low-Voltage Differential Signaling) Line Driver which accepts and converts LVTTL/LVCMOS input levels into LVDS output signals. The device is perfect for low-power low-noise applications requiring high signaling rates and reduced EMI emissions. The device is guaranteed to transmit data at speeds up to 800Mbps (400MHz) over controlled impedance media of approximately 100. Supported transmission media are PCB traces, backplanes, and cables. The AS1156 is a single LVDS transmitter, and the AS1154 is a dual LVDS transmitter. Outputs conform to the ANSI TIA/EIA-644 LVDS standards. Flow-through pinout simplifies PC board layout and reduces crosstalk by separating the LVTTL/LVCMOS inputs and LVDS outputs. The AS1156/AS1154 operates from a single +3.3V supply and is specified for operation from -40 to +85C.
2 Key Features
Flow-Through Pinout Guaranteed 800Mbps Data Rate 250ps Pulse Skew (Max) Conforms to ANSI TIA/EIA-644 LVDS Standards Single +3.3V Supply Operating Temperature Range: -40 to +85C 8-Pin SOIC Package
3 Applications
Digital Copiers, Laser Printers, Cellular Phone Base Stations, Add/Drop Muxes, Digital Cross-Connects, DSLAMs, Network Switches/Routers, Backplane Interconnect, Clock Distribution Computers, Intelligent Instruments, Controllers, Critical Microprocessors and Microcontrollers, Power Monitoring, and Portable/Battery-Powered Equipment.
Figure 1. Block Diagram
AS1156
AS1154
VCC
Tx
OUT1-
VCC
Tx
OUT1-
IN1
OUT1+
IN1
OUT1+
N/C
N/C
IN2
Tx
OUT2+
GND
N/C
GND
OUT2-
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AS1156/AS1154
Data Sheet - P i n o u t
4 Pinout
Pin Assignments
Figure 2. AS1156/AS1154 Pin Assignments (Top View)
VCC IN1 N/C GND
1 2
8 7
OUT1OUT1+ N/C N/C
VCC IN1 IN2 GND
1 2
8 7
OUT1OUT1+ OUT2+ OUT2-
AS1156
3 4 6 5 3 4
AS1154
6 5
Pin Descriptions
Table 1. AS1156/AS1154 Pin Descriptions Pin Number AS1154 1 2 3 4 5 6 7 8 7 8 3, 5, 6 4 AS1156 1 2 Pin Name VCC IN1 IN2 GND OUT2OUT2+ OUT1+ OUT1N/C Description Power Supply Input. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors. LVTTL/LVCMOS Driver Input LVTTL/LVCMOS Driver Input Ground Inverting LVDS Driver Output Noninverting LVDS Driver Output Noninverting LVDS Driver Output Inverting LVDS Driver Output Not connected
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AS1156/AS1154
Data Sheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter VCC to GND INx, EN, ENn to GND OUTx+, OUTx- to GND Short Circuit Duration (OUTx+, OUTx-) Continuous Power Dissipation (TA = +70C) Storage Temperature Range Maximum Junction Temperature Operating Temperature Range Limits -0.3 to +5.0 -0.3 to (VCC + 0.3) -0.3 to +5 Continuous 755 -65 to +150 +150 -40 to +85 mW
C C C
Units V V V
Notes
Derate 9.4mW/C Above +70C
Package Body Temperature
260
C
The reflow peak soldering temperature (body temperature) specified is in compliance with IPC/JEDEC J-STD020C "Moisture/ Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". Human Body Model, INx, OUTx+, OUTx--
ESD Protection
4
kV
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AS1156/AS1154
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
DC Electrical Characteristics
(VCC = +3.0 to +3.6V, TA = -40 to +85C , RL = 100 1% Typical values are at VCC = +3.3V, TA = +25C, Unless Otherwise Noted.) 1 Table 3. DC Electrical Characteristics Parameter LVDS Output (OUtx+, OUTx-) Differential Output Voltage
Change in Magnitude of VOD Between Complementary Output States VOD
Symbol
Conditions
Min
Typ
Max
Unit
Figure 21 on page 11 Figure 21 on page 11 Figure 21 on page 11 Figure 21 on page 11
250
355 1
450 35 1.375 25 1.6
mV mV V mV V V
VOD
VOS
Offset Voltage
Change in Magnitude of VOS Between Complementary Output States
1.125
1.25 4
VOS
VOH VOL IOSD IOS IOFF
Output High Voltage Output Low Voltage Differential Output Short-Circuit Current 2 Output Short-Circuit Current Power-Off Output Current Inputs (INx) High-Level Input Voltage Low-Level Input Voltage Input Current Supply Current No-Load Supply Current
0.90
VOD = 0V OUTx+ = 0V at INx = VCC or OUTx- = 0V at INx = 0V VCC = 0V or open, OUTx+ = 0V or 3.6V OUTx- = 0V or 3.6V, RL =
-9 -3.7 -20 -9 20
mA mA A
VIH VIL IIN INx = 0V or VCC RL = , INx = VCC or 0V for all channels RL = 100, INx = VCC or 0V for all channels, AS1156 RL = 100, INx = VCC or 0V for all channels, AS1154
2.0 GND -20
VCC
V V A
0.8 20
ICC
2 5.5 8.5
3.5 7.5 12
mA mA mA
Loaded Supply Current
ICCL
Notes: 1. Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except VOD. 2. Guaranteed by correlation data.
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AS1156/AS1154
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Switching Characteristics
(VCC = +3.0 to +3.6V, RL = 100 1%, CL = 2.5pF (differential), TA = -40 to +85C Typical values are at VCC = +3.3V, TA = +25C, Unless Otherwise Noted.) 1, 2, 3, 10
Table 4. Switching Characteristics Parameter Differential Propagation Delay, High-to-Low Differential Propagation Delay, Low-to-High Differential Pulse Skew 4 Differential Channel-to-Channel Skew 5 Differential Part-to-Part Skew 6 Differential Part-to-Part Skew 7 Rise Time Fall Time Maximum Operating Frequency 8, 9 Notes: 1. Parameters are guaranteed by design and characterization. 2. CL includes probe and jig capacitance. 3. Signal generator conditions for dynamic tests: VOL = 0, VOH = 2.4V, f = 100MHz, 50% duty cycle, RO = 50, tR 1ns, tF 1ns (0 to 100%). 4. tSKD1 is the magnitude difference of differential propagation delay. tSKD1 = |tPHLD - tPLHD|. 5. tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on the same device. 6. tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and within 5C of each other. 7. tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply and temperature ranges. 8. fMAX signal generator conditions: VOL = 0, VOH = 2.4V, 50% duty cycle, RO = 50, tR 1ns, tF 1ns (0 to 100%). 9. Transmitter output criteria: duty cycle = 45 to 55%, VOD 250mV. 10. For optimum performance matched circuits should be used. Symbol tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL fMAX Conditions Figure 20 on page 11 and Figure 21 on page 11 Figure 20 on page 11 and Figure 21 on page 11 Figure 20 on page 11 and Figure 21 on page 11 Figure 20 on page 11 and Figure 21 on page 11 Figure 20 on page 11 and Figure 21 on page 11 Figure 20 on page 11 and Figure 21 on page 11 Figure 20 on page 11 and Figure 21 on page 11 Figure 20 on page 11 and Figure 21 on page 11 200 200 400 356 352 Min 1.1 1.1 Typ 1.268 1.267 90 110 Max 1.5 1.5 200 250 750 900 800 800 Unit ns ns ps ps ps ps ps ps MHz
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AS1156/AS1154
Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
VCC = +3.3V, CLOAD = 2.5pF (differential), Freq = 20MHz, Tamb = +25C, unless otherwise noted Figure 3. Transition Time vs. VCC
270
Figure 4. Transition Time vs. Temperature
350
.
.
tTHL
300
tTHL
Transition Time (ps)
Transition Time (ps)
260
250 200 150 100 50 0 -50
tTLH
250
240
tTLH
230 3 3.1 3.2 3.3 3.4 3.5 3.6
-30
-10
10
30
50
70
90
Supply Voltage(V)
Ambient Temperature(C)
Figure 5. Differential Pulse Skew vs. VCC
80
Figure 6. Pulse Skew vs. Temperature
35 30
.
70
Differential Pulse Skew (ps)
60 50 40 30 20 10 0 3 3.1 3.2 3.3 3.4 3.5 3.6
. Pulse Skew (ps)
25 20 15 10 5 0 -50
-30
-10
10
30
50
70
90
Supply Voltage(V)
Ambient Temperature(C)
Figure 7. Differential Propagation Delay vs. VCC;
1.05
Figure 8. Differential Propagation Delay vs. Temp.
1.14
.
.
1.12 1.03
tPHLD
Diff. Propagation Delay (ns)
Diff. Propagation Delay (ns)
1.1 1.08 1.06 1.04 1.02 1 0.98 -50
tPHLD tPLHD
1.01
0.99
0.97
tPLHD
0.95 3 3.1 3.2 3.3 3.4 3.5 3.6
-30
-10
10
30
50
70
90
Supply Voltage(V)
Ambient Temperature(C)
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AS1156/AS1154
Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 9. Differential Output Voltage vs. VCC
350
Figure 10. Differential Output Voltage vs. Frequency
350 300 250 200 150 100 50 0 0 50 100 150 200 250 300 350 400
.
345
340
335
330
325 3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage (V)
Differential Output Voltage (mV)
Differential Output Voltage (mV)
.
Frequency (MHz)
Figure 11. Offset Voltage vs. VCC
1.24
Figure 12. Offset Voltage vs. Frequency
1.35
Offset Voltage (V) .
1.23
Offset Voltage (V) .
3 3.1 3.2 3.3 3.4 3.5 3.6
1.3
1.25
1.22
1.2
1.21
1.15 1.2
1.1 0 50 100 150 200 250
Supply Voltage (V)
Frequency (MHz)
Figure 13. Output Voltage vs. VCC;
1.45
VOUT+
Figure 14. Output Voltage vs. Load Resistance;
1.45
Output Voltage (V) .
Output Voltage (V) .
1.35
1.35
VOUT+
1.25
1.25
1.15
VOUT-
1.15
VOUT-
1.05
1.05
0.95 3 3.1 3.2 3.3 3.4 3.5 3.6
0.95 80 90 100 110 120 130 140 150
Supply Voltage (V)
Load Resistance ( )
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AS1156/AS1154
Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 15. ICC vs. VCC
11
Figure 16. ICC vs. Temperature;
13
.
10.6
.
12
Supply Current (mA)
10.2
Supply Current (mA)
Freq = 100MHz
11
9.8
10
Freq = 20MHz
9.4
9
9 3 3.1 3.2 3.3 3.4 3.5 3.6
8 -50
-30
-10
10
30
50
70
90
Supply Voltage (V)
Ambient Temperature(C)
Figure 17. Short Circuit Current vs. VCC
3.9
Figure 18. ICC vs. Frequency
18 16
Output Short Circuit Current (mA) .
3.85 3.8
. Supply Current (mA)
14 12 10 8 6 4 2 0 3 3.1 3.2 3.3 3.4 3.5 3.6 0 50 100 150 200 250
One Channel
Two Channels
3.75 3.7
3.65 3.6
Supply Voltage(V)
Frequency (MHz)
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AS1156/AS1154
Data Sheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
LVDS Interface
The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The AS1156/AS1154 is an 800Mbps single/dual differential LVDS driver that is designed for high-speed, point-to-point, low-power applications. This device accepts LVTTL/LVCMOS input levels and translates them to LVDS output signals. The AS1156/AS1154 generates a 2.5mA to 4.5mA output current using a current-steering configuration. This current steering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The driver outputs are short-circuit current limited, and enter a high-impedance state when the device is not powered or is disabled. The current-steering architecture of the AS1156/AS1154 requires a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor at the input of an LVDS receiver (AS1157, AS1158). Logic states are determined by the direction of current flow through the termination resistor. With a typical 3.7mA output current, the AS1156/AS1154 produces an output voltage of 370mV when driving a 100 load.
Termination
Because the AS1156/AS1154 is a current-steering device, no output voltage will be generated without a termination resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage levels depend upon the value of the termination resistor. The AS1156/AS1154 is optimized for point-to-point interface with 100 termination resistors at the receiver inputs. Termination resistance values may range between 90 and132, depending on the characteristic impedance of the transmission medium.
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AS1156/AS1154
Data Sheet - A p p l i c a t i o n s
9 Applications
Table 5. Function Table Input INx L H 0.8V < VINx < 2.0V OUTx+ L H Undetermined Output OUTxH L Undetermined
Figure 19. Typical Application Circuit
+3.3V
+3.3V
0.001F
0.1F
0.001F
0.1F
LVDS Signals LVTTL/LVCMOS Data Inputs LVTTL/LVCMOS Data Outputs
Tx
107
Rx
AS1156
AS1158 Single LVDS Receiver
100 Shielded Twisted Cable or Microstrip PC Board Traces
Power-Supply Bypassing
To bypass VCC, use high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to pin VCC.
Differential Traces
Input trace characteristics can adversely affect the performance of the AS1156/AS1154. Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor is also matched to this characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running the differential traces near each other. Reduce skew by using matched trace lengths. Tight skew control is required to minimize emissions and proper data recovery of the devices. Route each channel's differential signals very close to each other for optimal cancellation of their respective external magnetic fields. Use a constant distance between the differential traces to avoid irregularities in differential impedance. Avoid 90 turns (use two 45 turns). Minimize the number of vias to further prevent impedance irregularities.
Cables and Connectors
Supported transmission media include printed circuit board traces, backplanes, and cables. Use cables and connectors with matched differential impedance (typically 100) to minimize impedance mismatches. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.
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AS1156/AS1154
Data Sheet - A p p l i c a t i o n s
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length. Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals. Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent coupling. Separate the input LVDS signals from the output signals planes with the power and ground planes for best results. Figure 20. Driver Propagation Delay and Transition Time Waveforms
1.5V INx tPLHD OUTx0 Differential OUTx+
1.5V
tPHLD VOH 0
VOL
80% 0 20% VDIFF = (VOUTx+) - (VOUTx-)
80% 00 20%
tTLH
tTHL
Figure 21. Driver Propagation Delay and Transition Time Test Circuit
OUTx+
Generator 50
CL
RL
OUTx-
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AS1156/AS1154
Data Sheet - A p p l i c a t i o n s
Figure 22. Driver VOD and VOS Test Circuit
OUTx+
RL/2 VCC INx GND RL/2 VOS VOD
OUTx-
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AS1156/AS1154
Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
10 Package Drawings and Markings
The AS1156/AS1154 is available in a 8-pin SOIC package. Figure 23. 8-pin SOIC Package
Notes: 1. Lead coplanarity should be 0 to 0.10mm (.004") max. 2. Package surface finishing: - Top, matte (charmilles #18-30) - All sides, matte (charmilles +18-30) - Bottom, smooth or matte (charmilles +18-30) 3. All dimensions excluding mold flashes and end flash from the package body shall not exceed 0.25mm (.010") per side. 4. Details of pin #1 mark are optional but must be located within the area indicated.
Symbol A A1 A2 B C D E e H h L ZD
Min Max 1.52 1.72 0.10 0.25 1.37 1.57 0.36 0.46 0.19 0.25 4.80 4.98 3.81 3.99 1.27BSC 5.80 6.20 0.25 0.50 0.41 1.27 0 8 0.53REF
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AS1156/AS1154
Data Sheet - O r d e r i n g I n f o r m a t i o n
11 Ordering Information
Part Number AS1156-BSOU AS1156-BSOT AS1154-BSOU AS1154-BSOT Description Single Channel LVDS Line Driver Single Channel LVDS Line Driver Dual Channel LVDS Line Driver Dual Channel LVDS Line Driver Delivery Form Tubes Tape and Reel Tubes Tape and Reel Package SOIC-8 SOIC-8 SOIC-8 SOIC-8
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AS1156/AS1154
Data Sheet
Copyrights
Copyright (c) 1997-2008, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact
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